Scalable Hardware Mechanisms for Superscalar Processors

of the Dissertation Scalable Hardware Mechanisms for Superscalar Processors by Steven Daniel Wallace Doctor of Philosophy in Electrical and Computer Engineering University of California, Irvine, 1997 Professor Nader Bagherzadeh, Chair Superscalar processors fetch and execute multiple instructions per cycle. As more instructions can be executed per cycle, an accurate and high bandwidth instruction fetching mechanism becomes increasingly important to performance. This dissertation describes and analyzes instruction fetching mechanisms using three different cache types: a simple cache, an extended cache, and a self-aligned cache. A mathematical model is developed for each cache technique, and performance is evaluated both in theory and in simulation using the SPEC95 suite of benchmarks. In all the techniques, the fetching performance is dramatically lower than ideal expectations. Prefetching can be used to increase performance. Nevertheless, single block fetching performance is fundamentally limited by control transfers. Thus, to overcome this limitation, multiple blocks must be fetched in a single cycle. Accurate branch prediction and instruction fetch prediction of a microprocessor are also critical to achieve high performance. In order to achieve a high fetching rate for wideissue superscalar processors, a scalable method to predict multiple branches per block of